1. Field of the Invention
The present invention relates to a semiconductor device having in addition to a normal electronic circuit a spare electronic circuit which is used in the event of failure of the normal electronic circuit and used when the logic design is changed, and relates to a method of manufacturing such a semiconductor device.
2. Description of the Background Art
A semiconductor device provided with a spare electronic circuit has conventionally been used. When any failure of a normal electronic circuit or any mistake in a logic design of the entire semiconductor device is discovered by inspection, the spare electronic circuit is substituted for the failed normal electronic circuit or added between normal electronic circuits by just changing metal interconnections, only the spare electronic circuit then connected to other normal electronic circuits, so as to improve the yield of the semiconductor device.
A conventionally used semiconductor device having a spare electronic circuit in addition to a normal electronic circuit is hereinafter described in conjunction with FIGS. 13 to 15. The conventional semiconductor device having a spare electronic circuit has, for example, an inverter circuit 108aand an NAND circuit 109a at a semiconductor substrate 101 as normal electronic circuits as shown in FIGS. 13 and 14. Between inverter circuit 108a and NAND circuit 109a at semiconductor substrate 101, an inverter circuit 108b is provided as a spare which is used as a spare electronic circuit for inverter circuit 108a or used for changing the logic design of the entire electronic circuit.
Circuit element formation regions 101a and 101b are formed at inverter circuit 108a. Contact plugs 103 are connected to the source/drain regions of element formation regions 101a and 101b. A gate electrode 102a is provided to element formation regions 101a and 101b to be located between the source/drain regions.
Circuit element formation regions 101c and 101f are formed at spare inverter circuit 108b. Contact plugs 103 are connected to the source/drain regions of element formation regions 101c and 101f. A Gate electrode 102b is provided to element formation regions 101c and 101f to be located between the source/drain regions.
Circuit element formation regions 101d and 101e are formed at NAND circuit 109a. Contact plugs 103 are connected to the source/drain regions of element formation regions 101d and 101e. Gate electrodes 102c and 102d are formed at element formation regions 101d and 101e to be located between the source/drain regions.
Contact plugs 104a, 104b, 104c and 104d are respectively provided at gate electrodes 102a, 102b, 102c and 102d for connecting gate electrodes 102a, 102b, 102c and 102d with first metal interconnections located in an upper layer. At the upper ends of contact plugs 104a, 104b, 104c and 104d, first metal interconnections 105a, 105b, 105c and 105d are formed that extend laterally in FIG. 13 at a substantially constant height from a main surface of the semiconductor substrate. Outside the region where inverter circuit 108a, spare inverter circuit 108b and NAND circuit 109a are formed, a first metal interconnection 105e is formed which laterally extends in FIG. 13 to connect inverter circuit 108a with NAND circuit 109a.
Second metal interconnections 107a, 107b, 107c, 107d, 107e, 107f, 107g, 107h and 107i are formed in a layer which is located at a greater height from the substrate than the layer where the first metal interconnections 105a, 105b, 105c and 105d are formed. Plugs 106a, 106d, 106e, 106f, 106g, 106h and 106i are formed in order to connect the first metal interconnections 105a, 105b, 105c and 105d with the second metal interconnections 107a, 107b, 107c, 107d, 107e, 107f, 107g, 107h and 107i. These first metal interconnections, plugs and second metal interconnections are formed in an insulating film 200.
In this conventional semiconductor device thus provided with spare inverter circuit 108b, if inverter circuit 108a as a normal electronic circuit fails or when logic design is corrected by adding spare inverter circuit 108b, spare inverter circuit 108b can be utilized. When spare inverter circuit 108b is employed, limited layers such as the first metal interconnections, the plugs and the second metal interconnections are changed so as to replace inverter circuit 108a with spare inverter circuit 108b or to add spare inverter circuit 108b between inverter circuit 108a and NAND circuit 109a, and accordingly repair or change in the electronic circuit structure of the semiconductor device is accomplished. This scheme is employed in order to reduce the manufacturing cost of the semiconductor device as well as the turn-around-time in the manufacturing process of the semiconductor device.
In the above-described conventional semiconductor device having the spare electronic circuit, the second metal interconnections 107a and 107b which are normal electronic circuit interconnections connected to normal electronic circuits pass through the region where spare inverter 108b is formed. Therefore, if any defect in the circuit design is detected by inspection, change in arrangement of the interconnections is inevitable as shown in FIG. 15 in which the second metal interconnections 107a and 107b, which pass through the region where spare inverter circuit 108b is formed and connect normal circuits with each other, are moved to another region so as to use spare inverter circuit 108b. Specifically, the second metal interconnection 107a is changed to second metal interconnections 107m, 107k, 107p and first metal interconnections 105k and 105m, and the second metal interconnection 107b is changed to second metal interconnections 107n, 107o and 107l and first metal interconnections 105l and 105n. As a result, the interconnection route is extended by the lengths of the first metal interconnections 105l, 105n, 105k and 105m. If the route made up of the first metal interconnections 105l, 105n, 105k and 105m is extremely long, there arises a remarkable difference between the lengths of the electronic circuit interconnections connecting the electronic circuits with each other respectively before the change in the interconnections and after that. This difference of the lengths causes a delay in a pulse which travels between electronic circuits. The delay in the pulse between normal electronic circuits then causes lag of response timing between one electronic circuit and another electronic circuit. Accordingly, if any change is made in the interconnections which is accompanied by change in the arrangement of electronic circuit interconnections established in the original design, the change in the interconnections could adversely influence the entire electronic circuit.
Further, if the required change in interconnections is accompanied by a remarkable change in normal electronic circuit interconnection routes, the normal electronic circuit interconnection routes could be located too close to each other as in the region near the second metal interconnections 107p and 107o. If the electronic circuit interconnections are extremely close to each other, they could exert adverse electrical effects on each other. Therefore, change in the interconnections which could cause closely located electronic circuit interconnection routes should be avoided. Consequently, it is impossible to easily find out changed interconnection routes which do not introduce the closely located electronic circuit interconnection routes, and thus a spare electronic circuit cannot be utilized easily.
According to the metal interconnection design of the current semiconductor integrated circuit, in the same layer, electronic circuit interconnections each having a substantially minimum width under a design rule are arranged with a substantially minimum space therebetween under the design rule. Because of this, in the stage of design to change the interconnections, there could be no space in the same layer, between existing metal interconnections which have already been fixed, where a metal interconnection is to be inserted which is newly provided after the change in the interconnections.
If there is no space for inserting electronic circuit interconnections in the same layer, the arrangement of a large number of normal electronic circuit interconnections should be changed. If a large number of normal electronic circuit interconnections are changed, change in interconnections in just one or two layers is not enough, and thus change in interconnections in many layers is required. Consequently, if a spare electronic circuit is used, a large number of spare masks where patterns after change in interconnections are formed could be necessary.